法国专利FR3036844A1 METHOD OF MANUFACTURING SEMICONDUCTOR ON INSULATION

专利PDF首页>>法国专利

专利附录

专利说明

权利要求

类似技术

同族专利

引用文献

法律状态

优先权

专利摘要:
The present invention relates to a method which is adapted to produce a semiconductor on insulator structure, such as a Ge (Si) on insulator structure or a Ge on insulator structure. According to the method, a multilayer structure comprising alternating layer pairs, comprising a silicon layer and a germanium layer optionally with silicon is deposited on a silicon substrate comprising a germanium buffer layer. The multilayer structure is completed by a silicon passivation layer. A cleavage plane is formed in the multilayer structure, and the multilayer structure is bonded to a handling substrate comprising a dielectric layer. The multilayer structure is cleaved along the cleavage plane so as to prepare a semiconductor-on-insulator structure comprising a semiconductor manipulation substrate, a dielectric layer, a silicon passivation layer, and at least a portion of the alternating layer pairs, comprising a silicon layer and a germanium layer optionally with silicon.
公开号:FR3036844A1
申请号:FR1654984
申请日:2016-06-01
公开日:2016-12-02
发明作者:Gang Wang；Shawn G Thomas
申请人:SunEdison Semiconductor Pty Ltd；
IPC主号:

专利说明:

[0001] BACKGROUND OF THE INVENTION This application claims priority over the Provisional US Patent Application Serial No. 62 / 169,173 filed on June 1, 2015. FIELD OF THE INVENTION The present invention relates generally to the subject matter of the present invention. the field of manufacturing semiconductor wafers. More specifically, the present invention relates to a method of forming a semiconductor-on-insulator structure, such as a Ge (Si) on insulator structure or a Ge on insulator structure.
[0002] BACKGROUND OF THE INVENTION Semiconductor wafers are generally prepared from a monocrystalline ingot (eg, silicon ingot) which is cut and sanded to have one or more homogeneous surfaces or notches for orientation. correct slice in the following procedures. The ingot is then sliced into individual slices. Although silicon semiconductor wafers are currently referred to, other materials can be used to prepare semiconductor wafers, such as germanium, silicon carbide, silicon-germanium gallium arsenide, and other alloys of group III and group V elements, such as gallium nitride or indium phosphide, or alloys of group II and group IV elements, such as cadmium sulphide or zinc oxide. Semiconductor wafers (eg, silicon wafers) can be used in the preparation of composite layer structures. A composite layer structure (e.g., a semiconductor on insulator structure, and more specifically, a silicon on insulator (SOI) structure) generally comprises a wafer or a manipulation layer, a component layer, and a film (typically a insulating (i.e. dielectric) oxide layer between the handling layer and the component layer. Generally, the component layer has a thickness of between 0.01 and 20 microns, for example a thickness of between 0.05 and 20 microns. Thick film component layers may have a component layer thickness of from about 1.5 microns to about 20 microns. Thin film component layers may have a thickness of from about 0.01 micrometer to about 0.20 micrometer. In general, composite layer structures, such as silicon on insulator (SOI), silicon on sapphire (SOS), and silicon on quartz, are produced by placing two slices in close contact, thereby initiating bonding. by van der Waal forces, followed by a heat treatment to strengthen the link. Annealing can convert the terminal silanol groups to siloxane bonds between the two interfaces, so as to strengthen the bond. After thermal annealing, the bonded structure undergoes additional treatment to remove a substantial portion of the donor wafer to obtain a layer transfer. For example, slice thinning techniques, for example, etching or sanding, can be used, often referred to as back-engraved SOI (i.e., BES01), in which a silicon wafer is linked to the handling wafer and then slowly etched until only a thin layer of silicon remains on the wafer. See, for example, U.S. Patent No. 5,189,500. This process is time consuming and expensive, wastes one of the substrates, and generally does not produce a uniformity of thickness suitable for layers having a thickness of less than a few microns. Another common method for obtaining layer transfer is hydrogen implantation followed by thermally induced layer separation. Particles (ionized atoms or atoms, for example, hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth below the front surface of the donor wafer. The implanted particles form a cleavage plane in the donor wafer at the specified depth to which they have been implanted. The surface of the donor wafer is cleaned to remove organic compounds or other contaminants, such as boron compounds, deposited on the wafer during the implantation process. The front surface of the donor wafer is then bonded to a manipulative wafer to form a bonded wafer by a hydrophilic bonding process.
[0003] Prior to binding, the donor wafer and / or the manipulation wafer are activated by exposing the wafer surfaces to a plasma containing, for example, oxygen or nitrogen. Plasma exposure modifies the surface structure in a process often referred to as surface activation, said activation process rendering the surfaces of one or both of the donor wafer and the wafer surface hydrophilic. The wafer surfaces may further be chemically activated by wet treatment, such as SC1 cleaning or hydrofluoric acid. The wet treatment and the plasma activation can be carried out in any order, or the slices can be subjected to a single treatment. The slices are then pressed together, and a bond is formed therebetween. This bond is relatively weak due to the van der Waal forces and needs to be strengthened before further processing can be conducted. In some methods, the hydrophilic bond between the donor wafer and the manipulation wafer (i.e., a bonded wafer) is enhanced by heating or annealing the bonded pair of wafers. In some processes, the wafer bond can be conducted at low temperatures, for example between approximately 300 ° C and 500 ° C. The elevated temperatures cause the formation of covalent bonds between the junction surfaces of the donor wafer and the manipulation wafer, thereby solidifying the bond between the donor wafer and the wafer. Simultaneously with the heating or annealing of the bonded wafer, previously implanted particles in the donor wafer weaken the cleavage plane. A portion of the donor wafer is then separated (i.e., cleaved) along the cleavage plane from the bonded wafer to form the SOI wafer. Cleavage may be effected by placing the bonded wafer in a device in which a mechanical force is applied perpendicularly to opposite sides of the bonded wafer to remove a portion of the bond wafer from the bonded wafer. According to some methods, suction cups are used to apply the mechanical force. The separation of the portion of the donor wafer is initiated by applying a mechanical wedge to the edge of the wafer bonded to the cleavage plane in order to initiate the propagation of a crack along the cleavage plane. The mechanical force applied by the suction cups then removes the portion of the donor wafer from the bonded wafer, so as to form an SOI wafer.
[0004] According to other methods, the bonded pair may instead be subjected to elevated temperature for a period of time to separate the portion of the donor wafer from the bonded wafer. High temperature exposure causes crack initiation and propagation along the cleavage plane, thereby separating a portion of the donor wafer. The crack is formed due to the formation of voids from implanted ions, which grow by Ostwald maturation. The voids are filled with hydrogen and helium. The voids become slats. Pressurized gases in the lamellae propagate microcavities and microcracks, which weaken the silicon on the implantation plane. If the annealing is stopped at the appropriate time, the weakened bonded wafer may be cleaved by a mechanical process. However, if the heat treatment is extended for a longer time and / or at a higher temperature, the propagation of microcracks reaches the level at which all cracks merge along the cleavage plane, thereby separating a portion of the donor wafer. This method allows for better uniformity of the transferred layer and allows for recycling of the donor wafer, but typically requires heating of the implanted and bonded pair at temperatures close to 500 ° C. Silicon-germanium-on-insulator substrates (SG01) are frequently manufactured by germanium condensation or layer transfer of a silicon-germanium layer from an epitaxially deposited silicon-germanium buffer layer formed on a substrate. in silicon. In the Ge condensation approach, an epitaxial layer of SiGe under stress is formed on Si on insulator (SOI). See T. Tezuka, et al., APL 79, p1798 (2001). The Ge concentration of the SiGe epitaxial layer is generally in the range of 10 to 30%. After epitaxial deposition of a silicon-germanium layer, the wafer is treated in an oven with different thermal cycles in an ambient atmosphere of O 2 in order to preferentially oxidize the silicon. Between oxidation cycles, annealing in an ambient argon atmosphere is frequently used to allow Ge diffusion and homogenize the layer. The high densities of stacking faults generated by the dissociation of through dislocations due to SiGe layer stress relaxation during Ge condensation is a disadvantage of this approach.
[0005] Alternatively, a SiGe thin film is transferred from a stress relieving SiGe buffer layer using the Smart Cut technique. See Fitzgerald, 3036844 5 Solid-State Electronics 48 (2004) 1297-1305. The layer quality of the transferred SiGe layer is determined by the SiGe epitaxial layer formed on the donor substrate. Research to date has shown that it is very difficult to obtain a high quality stress relieving SiGe buffer layer. In order to take advantage of the greater carrier mobility in the SiGe layer with respect to a silicon layer, the Ge concentration in the SiGe layer must be greater than 50%, preferably greater than 80%. The high density of through dislocations (-10 "through-dislocations per cm2) in SiGe stress relieving buffers with a high concentration of 10 Ge and the rough surface (Rms in the range of 2 to 50 nm) caused by Dense through dislocations degrade the quality of the transferred SiGe layer and complicate the layer transfer process In addition, the residual stress in the SiGe buffer layer leads to high slice camber, especially for 300 mm slices, which causes processing problems in wafer bonding and layer transfer SUMMARY OF THE INVENTION Briefly, the present invention relates to a process for preparing a multilayered structure.The process comprises (a) the deposition of a first layer comprising germanium on a front surface of a silicon substrate, the silicon substrate comprising two major surfaces, generally parallel, 25 one of which is the front surface of the silicon substrate and the other of which is a back surface of the silicon substrate, a circumferential edge joining the front and rear surfaces of the silicon substrate, a central plane between and parallel to the front surface and the back surface of the silicon substrate, a central axis perpendicular to the central plane, and a volume region between the front and back surfaces of the silicon substrate, and further wherein the first layer comprising germanium has a thickness of between about 0.5 micrometer and about 100 micrometers, as measured along the central axis; (b) depositing a second layer comprising silicon on the first layer comprising germanium, the second layer comprising silicon having a thickness of between about 0.5 nanometers and about 5 nanometers, as measured along the central axis; and (c) depositing a third layer comprising germanium and optionally silicon on the second layer comprising silicon, the third layer comprising silicon and germanium having a formula SixGei_x, wherein x is between about 0 and about 0.8, in mole ratio and further the third layer comprising silicon and germanium having a thickness of at least about 1 nanometer. The present invention further relates to a method of preparing a semiconductor on insulator structure. The method comprises forming a cleavage plane in a multilayer structure, the multilayer structure comprising (i) a silicon substrate comprising two major, generally parallel surfaces, one of which is a front surface of the silicon substrate and whose the other is a back surface of the silicon substrate, a circumferential edge joining the front and rear surfaces of the silicon substrate, a central plane between and parallel to the front surface and the rear surface of the silicon substrate, a perpendicular central axis at the central plane, and a volume region between the front and back surfaces of the silicon substrate, (ii) a germanium layer in interfacial contact with the front surface of the silicon substrate, (iii) at least one pair of layers in interfacial contact with the germanium layer, each pair of layers comprising a silicon layer and a layer comprising germanium and optionally silicon having a has the formula SixGel_x, wherein x is from about 0 to about 0.8, in mole ratio, and (iv) a silicon passivation layer in contact with at least one pair of layers, wherein the cleavage plane is formed in at least one pair of layers comprising the silicon layer and the silicon-germanium layer; and bonding the multilayer structure at an interfacial dielectric layer contact with a front surface of a semiconductor manipulation substrate, the semiconductor manipulation substrate comprising two major, generally parallel surfaces, of which one is the front surface of the semiconductor handling wafer and the other is a back surface of the semiconductor manipulation substrate, a circumferential edge joining the front and rear surfaces of the semiconductor handling substrate. -conductor, and a volume region between the front and rear surfaces of the semiconductor handling substrate. The present invention further relates to a multilayer structure comprising: (i) a silicon substrate comprising two major, generally parallel, surfaces, one of which is a front surface of the silicon substrate and the other of which is a rear surface 3036844 silicon substrate, a circumferential edge joining the front and rear surfaces of the silicon substrate, a central plane between and parallel to the front surface and the rear surface of the silicon substrate, a central axis perpendicular to the central plane, and a volume region. between the front and back surfaces of the silicon substrate, (ii) a germanium layer in interfacial contact with the front surface of the silicon substrate, (iii) at least one pair of layers in interfacial contact with the germanium layer, each layer pair comprising a silicon layer and a layer comprising germanium and optionally silicon having a formula SixGei_x, wherein x is between about 0 and about 0.8, in molar ratio, and (iv) a silicon passivation layer in contact with the at least one pair of layers. Other objects and features of this invention will become apparent in part and are partially described hereinafter.
[0006] BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A-1E describe an exemplary process scheme for making a multilayer silicon-germanium donor structure according to embodiments of the method of the present invention. Fig. 2 depicts an exemplary process scheme for making a silicon-germanium-on-insulator (SG01) structure according to embodiments of the method of the present invention.
[0007] DETAILED DESCRIPTION OF THE EMBODIMENT (S) OF THE INVENTION According to some embodiments of the present invention, a method is disclosed for producing a semiconductor on insulator (SOI) structure, and more specifically a silicon structure. -germanium on insulator (SG01). In some embodiments, a buffer layer comprising Ge is deposited on a silicon substrate, for example, a silicon wafer, and more specifically a monocrystalline silicon wafer. The buffer layer allows consecutive deposition of one or more layers of Ge or SiGe of high quality. The deposition of a layer of Ge or SiGe is followed by the deposition of a thin layer of silicon. The deposition process of a layer of Ge or SiGe, followed by deposition of a thin silicon layer 3036844 can be repeated one or more times, for example, two, three, four, five, six, seven, eight times or more, so as to form a multilayer stack of layers of Ge or SiGe and silicon alternating. The high quality silicon-germanium layers can be ion implanted and bonded to a manipulative substrate and subjected to a cleavage technique to make an SGOI. Substrates With reference to FIG. 1A, a substrate for use in the process of the present invention may comprise a semiconductor substrate 10, such as a silicon substrate, for example, a silicon wafer, and more specifically a silicon wafer. monocrystalline silicon wafer. In general, the semiconductor substrate 10 comprises two major, generally parallel surfaces 12, 14. One of the parallel surfaces is a front surface 12 of the wafer, and the other parallel surface is a back surface 14 of the wafer. The semiconductor substrate 10 includes a circumferential edge 16 assembling the front surface 12 and the rear surface 14, a volume region 18 between the front surface 12 and rear surface 16, 20 and a central plane 20 between the front and rear surfaces. The semiconductor substrate 10 further comprises an imaginary central axis 22 perpendicular to the central plane 22 and a radial length 24 extending from the central axis 22 to the circumferential edge 16. In addition, since for example, silicon wafers, typically have a total thickness variation (TTV), warp and camber, the center point between each point on the front surface and each point on the back surface may not be to be located precisely in a plane. In practice, however, the TTV, warping and camber are typically so small that, in a narrow approximation, it can be said that the center points are located in an imaginary central plane which is approximately equidistant between the front surfaces and back. Before any operation of the present invention, the front surface 12 and the rear surface 14 of a semiconductor substrate 10 may be substantially identical. A surface is referred to as a "front surface" or "back surface" only for the sake of convenience and generally to distinguish the surface on which the process operations of the present invention are carried out. In the context of the present invention, a "front surface" of a semiconductor substrate 10, for example, a monocrystalline silicon wafer, refers to the major surface on which the process steps of the present invention are carried out.
[0008] The semiconductor substrate 10 may be a monocrystalline semiconductor wafer. In preferred embodiments, the semiconductor wafers comprise a semiconductor material selected from the group consisting of silicon, silicon carbide, sapphire, aluminum nitride, silicon germanium, gallium arsenide, gallium nitride, phosphide, and the like. indium, indium gallium arsenide, germanium, and combinations thereof. The monocrystalline semiconductor wafers of the present invention typically have a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. The wafer thicknesses can range from about 250 micrometers to about 1500 micrometers, for example, from about 300 micrometers to about 1000 micrometers, suitably in the range of about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers.
[0009] In particularly preferred embodiments, the semiconductor substrate 10 comprises a monocrystalline silicon wafer which has been sliced from a monocrystalline ingot formed according to conventional Czochralski crystal growth methods or methods of growth. floating area. Such methods, as well as standard techniques for slicing, etching, etching and polishing silicon are described, for example, in F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989, and Silicon Chemical Etching, (J. Grabmaier Ed.) Springer-Verlag, NY, 1982. Preferably, the slices are polished and cleaned by standard methods known to those skilled in the art. See, for example, W.C. O'Mara et al., Handbook of Semiconductor Silicon Technology, 30 Noyes Publications. If necessary, the slices can be cleaned, for example, in a standard SC1 / SC2 solution. In some embodiments, the monocrystalline silicon wafers of the present invention are monocrystalline silicon wafers that have been sliced from a monocrystalline ingot formed according to conventional Czochralski ("Cz") crystal growth methods, typically having a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm.
[0010] Preferably, the monocrystalline silicon handling wafer and the monocrystalline silicon wafer have a front surface with mirror-polished finishes that is free of surface defects, such as scratches, large particles, and the like. The wafer thickness may range from about 250 micrometers to about 1500 micrometers, for example, from about 300 micrometers to about 1000 micrometers, suitably in the range of about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers.
[0011] In some embodiments, the semiconductor substrate 10, for example, the monocrystalline silicon wafer comprises interstitial oxygen at concentrations that are generally obtained by the Czochralski growth method. In some embodiments, the semiconductor wafers comprise oxygen at a concentration of between about 4 PPMA and about 18 PPMA. In some embodiments, the semiconductor wafers comprise oxygen at a concentration of from about 10 PPMA to about 35 PPMA. Preferably, the monocrystalline silicon wafer comprises oxygen at a concentration of not more than about 10 ppma. Interstitial oxygen can be measured according to SEMI MF 1188-1105.
[0012] In general, there are no constraints on the resistivity of the SOI substrate handling slices. The semiconductor substrate 10 may have any resistivity obtainable by the Czochralski or floating area methods. Accordingly, the resistivity of the semiconductor substrate 10 is based on the requirements of the final use / application of the structure of the present invention. As a result, the resistivity can vary from milliohm or less to mega-ohm or higher. In some embodiments, the semiconductor substrate 10 comprises a p-type or n-type dopant. Suitable dopants include boron (type p), gallium (type p), phosphorus (type n), antimony (type n), and arsenic (type n). The dopant concentration is chosen on the basis of the desired resistivity of the handling wafer. In some embodiments, the monocrystalline semiconductor manipulation substrate comprises a p-type dopant. In some embodiments, the monocrystalline semiconductor handling substrate is a monocrystalline silicon wafer comprising a p-type dopant, such as boron.
[0013] In some embodiments, the semiconductor substrate 10 has a relatively low minimum volume resistivity, such as less than about 100 ohm-cm, less than about 50 ohm-cm, less than about 1 ohm-cm. cm, less than about 0.1 ohm-cm, or even less than about 0.01 ohm-cm. In some embodiments, the semiconductor substrate 10 has a relatively low minimum volume resistivity, such as less than about 100 ohm-cm, or between about 1 ohm-cm and about 100 ohm-cm. Low resistivity wafers may comprise electrically active dopants, such as boron (type p), gallium (type p), phosphorus (type n), antimony (type n), and arsenic (type n). ).
[0014] In some embodiments, the semiconductor substrate 10 has a relatively high minimum volume resistivity. High resistivity slices are generally sliced from monocrystalline ingots formed by the Czochralski process or floating zone. High resistivity wafers may comprise electrically active dopants, such as boron (p type), gallium (p type), aluminum (p type), indium (p type), phosphorus (n type). ), antimony (type n), and arsenic (type n), at generally very low concentrations. Cz-shaped silicon wafers can be thermally annealed at a temperature in the range of about 600 ° C to about 1000 ° C to suppress oxygen-caused thermal donors that are incorporated during crystalline growth. . In some embodiments, the monocrystalline semiconductor wafer has a minimum volume resistivity of at least 100 ohm-cm, at least about 500 ohm-cm, at least about 1000 ohm-cm, or even at least about 3000 ohm-cm, for example, from about 100 ohm-cm to about 100,000 ohm-cm, or from about 500 ohm-cm to about 100,000 ohm-cm, or from about 1000 ohm-cm to about 100,000 ohm-cm. cm, or between about 500 ohm-cm and about 10,000 ohm-cm, or between about 750 ohm-cm and about 10,000 ohm-cm, between about 1000 ohm-cm and about 10,000 ohm-cm, between about 2000 ohm and about 10,000 ohm-cm, from about 3000 ohm-cm to about 10,000 ohm-cm, or from about 3000 ohm-cm to about 5,000 ohm-cm. In some embodiments, the high resistivity monocrystalline semiconductor handling substrate may comprise a p-type dopant, such as boron, gallium, aluminum, or indium. In some embodiments, the high resistivity monocrystalline semiconductor handling substrate may comprise an n-type dopant, such as phosphorus, antimony, or arsenic. Methods for making high resistivity slices are known in the art, and such high resistivity slices can be obtained from commercial vendors, such as SunEdison Semiconductor Ltd. (St. Peters, MO; formerly MEMC Electronic Materials, Inc.).
[0015] The semiconductor substrate 10 may comprise monocrystalline silicon. The semiconductor substrate 10 may be any of a crystalline orientation (100), (110) or (111), and the choice of crystalline orientation may be governed by the end use of the structure. In some preferred embodiments, the semiconductor substrate 10 has a crystalline orientation (100) since the silicon-germanium layer of the present invention is adapted to replace the silicon component layers in a logic component. The use of silicon-germanium increases the switching speed of the logic component, and the crystal orientation (100) is generally used in CMOS components, such as logic components, since this crystal plane produces the best performance of component. With reference to FIG. 1A, the semiconductor substrate 10 comprises a central axis 22. The central axis 22 is specifically described in FIG. 1A since the "thickness" of the various layers of the substrate 10 and the layers 20 successively added according to the method of the present invention are measured along this central axis 22. Deposition and annealing of germanium According to the method of the present invention, and with reference to FIG. 1B, a layer 30 comprising germanium is deposited on the front surface 12 (FIG. 1A) of the semiconductor substrate 10. In certain embodiments, In one embodiment, the layer 30 comprising germanium is substantially pure germanium in that the precursors used to deposit the germanium layer do not include precursors that would deposit substantially other materials, for example, silicon. Accordingly, the layer 30 comprising germanium may comprise no more than trace amounts of other materials (less than about 1%, preferably less than about 0.1%, less than about 0.01%, or even less than about 0.001%). In other words, the layer 30 comprising germanium is at least about 95% Ge, at least about 98% Ge, at least about 99% Ge, at least about 99.99% Ge. or even at least about 3099844 99.999% of Ge. The germanium may be deposited in a layer 30 having a deposited thickness of between about 0.1 micrometre and about 100 micrometers as measured along the central axis 22, for example between about 0.5 micrometre and about 100 micrometers such that measured along the central axis 22, for example between about 0.5 micrometers and about 50 micrometers as measured along the central axis 22, or between about 1 micrometer and about 10 micrometers as measured along the the central axis 22.
[0016] The germanium layer 30 may be deposited by metallo-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD). ), plasma enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). Germanium can be deposited in a pulsed or continuous mode. In some embodiments, the germanium may be deposited by epitaxial deposition. Commercially available tools used for Ge deposition include, but are not limited to, ASM Epsilon E2000, ASM Epsilon E3200, Centura. Germanium can be deposited by epitaxial deposition using germanium precursors such as Gel-14, Ge21-14, GeC14, GeCl2, GeF2, GeF4, GeI2, GeI4, and combinations thereof. The ambient atmosphere of the chamber may further include a carrier gas, which may be inert or may be a reducing atmosphere. Suitable carrier gases include hydrogen, argon, helium, nitrogen, or any combination thereof. A preferred carrier gas, which is also a reagent, is hydrogen. The deposition temperature of the germanium layer may be from about 200 ° C to about 900 ° C, for example from about 200 ° C to about 800 ° C, for example from about 300 ° C to about 700 ° C, or between about 400 ° C and about 600 ° C. The ambient chamber pressure can be from about 10 Torr (about 1.33 kPa) to about 760 Torr (about 101.32 kPa), preferably from about 10 Torr (about 1.33 kPa) to about 100 Torr (about 13.33 kPa). In some embodiments of the present invention, after deposition of the germanium layer, the semiconductor substrate 10 comprising a layer 30 comprising germanium thereon is annealed so as to increase the mobility of the through dislocations and cause their removal. The crossing dislocations have a high mobility in Ge. Annealing 3036844 14 increases the probability that the through dislocations will slide through the Ge layer, where they will combine with each other or reach the surface, where they are removed. See Wang, and. al., APPLIED PHYSICS LETTERS 94, 102115 2009. In addition, the high mobility of the through dislocations in Ge prevents the formation of through dislocation stacks such as those typically observed in SiGe buffer layers. Annealing may reduce the density of through-dislocations in the germanium buffer layer to no more than about 1x107 through-dislocations / cm 2, such as no more than about 1x106 through-dislocations / cm 2.
[0017] In addition, the high mobility of the through dislocations in Ge inhibits or even prevents the formation of through dislocation stacks so as to reduce wafer deformation. Since there are no dislocation stacks in a Ge buffer layer, the residual stress in a stress relaxation Ge buffer is the stress due to the difference in thermal expansion coefficient (5, 9 ppm for Ge and 2.6 ppm for Si). In contrast, when a SiGe buffer is formed on Si substrates, the through dislocations are stacked or do not slip sufficiently to be suppressed because of its higher slip activation energy (-1.5 eV for Ge and 2.3 eV for SiGe). As a result, a stress associated with the high density of through dislocations in combination with the thermal stress leads to significant slice deformation. Increasing the Ge concentration in the SiGe buffer layer attenuates the slice deformation to a certain degree.
[0018] In addition, annealing can reduce surface roughness. The higher surface mobility of the Ge atoms leads to an improved surface roughness (root mean square, Rms, roughness of the order of 0.5 nm) of the buffer layer compared to a SiGe layer (RMS, Rms, roughness of the order of 1 to 20 nm). The root mean square as a measure of roughness is calculated by Rq = = 1 equation, where the roughness profile contains ordered points, evenly spaced along the trace, and y, is the vertical distance from the line median at the data point. Rms is typically measured over an area of 2x2 micrometer2. The smooth surface of the Ge buffer layer provides an excellent starting surface for subsequent growth of the Si etch stop layer or the SiGe top layer, and no chemical mechanical polishing process is required. as is the case when a buffer layer of SiGe is used.
[0019] In addition, the germanium buffer layer facilitates the growth of an upper layer of smooth Si and SiGe. When an Si or SiGe top layer is formed on a stress relaxation Ge buffer layer, the network difference between Si (SiGe) and Ge generates a tensile stress in the Si (SiGe) top layer. The tensile stress produces a driving force for surface smoothing during growth of the SiGe top layer. A smooth SiGe layer can be obtained by this approach, which is beneficial for the subsequent slice bonding process. The annealing may be conducted at a temperature of at least about 500 ° C, such as at least about 750 ° C, for example about 500 ° C to about 930 ° C, or about 750 ° C to about 900 ° C ° C. The annealing temperature should be below the melting point of germanium, which is 938.2 ° C. The ambient chamber pressure can range from about 10 Torr (about 1.33 kPa) to about 760 Torr (about 101.32 kPa), preferably from about 10 Torr (about 1.33 kPa) to about 100 Torr (about 100 Torr). (about 13.33 kPa). The ambient atmosphere of the chamber during annealing may comprise a carrier gas, which may be inert or may be a reducing atmosphere. Suitable gases include hydrogen, helium, nitrogen, argon or any combination thereof. The annealing time can be from about 1 second to about 60 minutes, for example from about 10 seconds to about 30 minutes. III. Silicon etch stop layer deposition In some embodiments and with reference to Fig. 1C, after deposition of a germanium buffer layer 30, an etch stop layer 40 comprising silicon may be deposited. on the germanium buffer layer 30. The etch stop layer 40 comprising silicon can be deposited by chemical-organic vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition ( CVD), low pressure vapor phase chemical deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). In some embodiments, silicon may be deposited by epitaxial deposition. Silicon precursors include methylsilane, silicon tetrahydride (silane), trisilane (Si3H8), disilane (S121-16), pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHCI3), silicon tetrachloride (SiCl4), among others.
[0020] In certain preferred embodiments, the silicon precursor is selected from silane, dichlorosilane (S1H2Cl2), and trichlorosilane (SiHCI3). The ambient atmosphere of the chamber may further include a carrier gas, which may be inert or may be a reducing atmosphere. Suitable carrier gases include hydrogen, argon, helium, nitrogen or any combination thereof. A preferred carrier gas, which is also a reagent, is hydrogen. In some embodiments, the deposition temperature may be from about 300 ° C to about 800 ° C, for example, from about 300 ° C to about 600 ° C, for example from about 400 ° C to about 500 ° C. The ambient chamber pressure can be from about 10 Torr (about 1.33 kPa) to about 15 760 Torr (about 101.32 kPa), preferably from about 10 Torr (about 1.33 kPa) to about 100 Torr (about 13.33 kPa). In some embodiments, the etch stop layer 40 comprising silicon has a thickness of between about 0.1 nanometers and about 50 nanometers, as measured along the central axis 22. In some embodiments the thickness may be between about 0.5 nanometers and about 20 nanometers, as measured along the central axis 22, or between about 0.5 nanometers and about 5 nanometers, as measured along the central axis 22.
[0021] The etch stop layer 40 comprising silicon between the Ge or SiGe layer and the Ge buffer layer is advantageous for forming a barrier layer during the SGOI finishing process. In addition, the etch stop layer 40 comprising silicon provides effective passivation between the SiGe component layer and the underlying insulator layer, typically SiO 2, in the final SGOI structure. IV. Ge-containing layer deposition (pure germanium layer or silicon-germanium layer) In some embodiments and with reference to FIG. 1D, after deposition of the germanium buffer layer 30 and the barrier layer etch 40 comprising silicon, a layer 50 comprising germanium, optionally with silicon, is deposited on the etch stop layer 40 comprising silicon. The layer comprising germanium, optionally with silicon, has a formula SixGel_x, in which x is between about 0.00 and about 0.8, in molar ratio, for example between about 0.1 and about 0.8, in molar ratio, for example between about 0.1 and about 0.4, in molar ratio. The layer 50 comprising germanium, optionally with silicon, can be deposited by metallo-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), chemical deposition in situ. low pressure vapor phase (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or molecular beam epitaxy (MBE). In some embodiments, silicon and germanium may be deposited by epitaxial deposition. Silicon precursors include methylsilane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHC13), silicon tetrachloride (SiC14), among others. In certain preferred embodiments, the silicon precursor is selected from silane, dichlorosilane (SiH2Cl2), and trichlorosilane (SiHC13). The germanium can be deposited by epitaxial deposition using germanium precursors selected from the group consisting of GeH4, Ge2114, GeCl4, and combinations thereof. The ambient atmosphere of the chamber may further include a carrier gas, which may be inert or may be a reducing atmosphere. Suitable carrier gases include hydrogen, argon, helium, nitrogen or any combination thereof. A preferred carrier gas, which is also a reagent, is hydrogen. The layer 50 comprising germanium, optionally with silicon, may be deposited at a deposition temperature which may be between about 200 ° C and about 800 ° C, for example between about 300 ° C and about 700 ° C. The ambient chamber pressure may be from about 10 Torr (about 1.33 kPa) to about 760 Torr (about 101.32 kPa), preferably from about 10 Torr (about 1.33 kPa) to about 100 Torr (about 1.30 kPa). Torr (about 13.33 kPa). In some embodiments, the layer 50 comprising germanium, optionally with silicon, has a thickness of between about 1 nanometer and about 1000 nanometers, as measured along the central axis 3036844 18 22. In some embodiments, embodiment, the thickness can be between about 5 nanometers and about 300 nanometers, as measured along the central axis 22. The thickness of the layer 50 comprising germanium, optionally with silicon, governs the thickness of the Ge or SiGe component layer on the final SGOI structure. V. Deposition of additional layers to prepare a stack of layers Referring hereinafter to FIG. 1E, the deposition steps of the silicon etch stop layer and the deposition layer comprising germanium, optionally with silicon, may be repeated, as described herein, to obtain a multilayer structure comprising two silicon etch layers 40, 60 and two layers 50, 70 comprising germanium, optionally with silicon. Depositing a pair of a silicon etch stop layer and a layer comprising germanium, optionally with silicon, may be repeated one or more times, i.e. twice, three times. times, four times, five times, six times, or more, so as to prepare a multilayer structure comprising multiple pairs of a silicon etch layer and a layer comprising silicon and germanium. V. Layer Transfer and Fabrication of Semiconductor-on-Insulator Structures (Ge01 or SG01 Structures) Referring to Fig. 2, the multilayer structure (designated 100 and 110 in Fig. 2) comprising at least one pair of a silicon etch stop layer and a layer comprising germanium, and optionally silicon, is a donor structure in the manufacture of a semiconductor on insulator 230, 330, 30 such as a germanium structure on insulator (Ge01) or silicon-germanium on insulator (SG01). As depicted in FIG. 2, the multilayer donor structure 100 starts the layer transfer process with four pairs of a silicon etch stop layer and a layer comprising germanium, optionally with silicon. The multilayer donor structure may comprise one or more, for example, at least two, three, four, five, six, seven or more pairs of a silicon etch stop layer and a layer comprising 3036844. germanium, optionally with silicon. After a first layer transfer operation, the multilayer donor structure 102 comprising a rough cleavage surface is subjected to wet chemical etching to remove the rough layer comprising germanium, and optionally silicon, and becomes the structure 103. The Etching agent used only etches the layer comprising germanium, and optionally silicon, selectively but does not etch the silicon etch stop layer. A suitable etching solution is a solution of H 2 O 2 (comprising between 0.1 and 1 mole of hydrogen peroxide per liter of distilled water). The etching operation may be performed in a standard semiconductor manufacturing cleaning device at room temperature or at elevated temperature (e.g., between 50 and 70 ° C). Depending on the etching agent concentration and the temperature, the typical etching time is in the range of 30 seconds to 10 minutes. A pair of layers comprising the etch stop layer 40 comprising silicon and the layer 50 comprising germanium, optionally with silicon of the starting multilayer donor structure 100 may be transferred to a handling substrate comprising a handling layer semiconductor 210 and a dielectric layer 220. The process may be repeated, one or more times, in which a pair of layers of the multilayer donor structure 110 may be transferred to a handling substrate comprising a semi-manipulation layer. -conductor 310 and a dielectric layer 320. After a second layer transfer operation, the resulting multi-layer donor structure 104 is subjected to another wet chemical etching to remove the rough layer comprising germanium, and optionally silicon, having the surface of rough cleavage. The layer transfer leads to the fabrication of a semiconductor on insulator structure 230, 330, such as a germanium on insulator (Ge01) or silicon-germanium on insulator (SG01) structure. According to some embodiments of the present invention, ions are implanted in multilayer structure 100 through a pair of layers comprising a silicon etch stop layer and a layer comprising germanium, optionally with silicon in the former. step of preparing a cleavage plane near a silicon etching layer. The ions are implanted at a depth sufficient for at least one pair of layers comprising a silicon etch layer and a layer comprising silicon and germanium to be transferred to a handling substrate.
[0022] Prior to ion implantation, the front surface of the multilayer structure may be thermally oxidized (where a portion of the deposited semiconductor material film is consumed) to prepare the semiconductor oxide film, or the film Semiconductor oxide (e.g., silicon dioxide) can be formed by CVD oxide deposition, such as PECVD or LPCVD. In some embodiments, the front surface of the multilayer structure may be thermally oxidized in an oven such as an A400 ASM in the same manner as described above. In some embodiments, the donor substrates are oxidized to form an oxide layer on the front surface layer of at least about 5 nanometers thick, for example between about 5 nanometers and about 1000 nanometers thick, or at least about 10 nanometers thick, for example between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, or between about 100 nanometers and about 800 nanometers, such as about 600 nanometers.
[0023] In addition, the oxide layer on the front surface of the multilayer structure may be subjected to chemical mechanical polishing (CMP) to reduce the surface roughness, preferably to the 2x2 micrometer RMS level which is less than about 5 angstroms, where the root mean square - Rq =, the roughness profile 20 contains ordered points, uniformly spaced along the trace, and y; is the vertical distance from the midline to the data point. Ion implantation may be conducted in a commercially available instrument, such as Applied Materials Quantum II, Quantum LEAP, or Quantum X. The implanted ions include He, H, H2, or combinations thereof. The ion implantation is conducted at a density and for a time sufficient to form a damage layer in the semiconductor donor substrate. The implantation density may be in the range of about 10 12 ions / cm 2 to about 10 17 ions / cm 2, such as from about 10 14 ions / cm 2 to about 10 17 ions / cm 2, such as about 10 15 ions / cm 2 at about 1016 ions / cm 2. The implantation energies may be in the range of about 1 keV to about 3,000 keV, such as from about 5 keV to about 1,000 keV, or from about 5 keV to about 200 keV, or from 5 keV to about 100 keV, or from 5 keV to about 80 keV. The implantation depth determines the amount of material transferred to a handling substrate. Preferably, the ion implantation depth is, as depicted in FIG. 2, sufficient to form a cleavage plane in a silicon-germanium layer so that the material transferred to the handling substrate comprises a layer of silicon-germanium. silicon etch stop, silicon-germanium layer, and another silicon etch stop layer. The insertion of the Si etch stop layer further leads to a fine cleavage plane and leads to the reduction of the surface roughness of the cleavage surface. The interfacial stress induced by the silicon etch stop layer at the interface between two adjacent layers comprising germanium, optionally with silicon, tends to trap implanted ions, such as H + or He +, which confine the cavities at the silicon etch stop layer. Cleavage is likely to occur along the silicon etch stop layer. In some embodiments of the present invention, the multilayer structure having an ion implantation region formed therein by the implantation of helium and / or hydrogen ions is annealed at a temperature sufficient to form a thermally activated cleavage plane. An example of a suitable tool may be a simple box furnace, such as a Blue M model. In some preferred embodiments, the structure is annealed at a temperature of about 200 ° C. at about 350 ° C, from about 225 ° C to about 325 ° C, preferably about 300 ° C. Thermal annealing may occur for about 10 minutes to about 10 hours, such as about 0.5 hours to about 4 hours, or about 2 hours to about 8 hours. Thermal annealing in this temperature range is sufficient to form a thermally activated cleavage plane.
[0024] According to the method of the present invention, the multilayer structure is bonded to a handling substrate 210. The manipulating substrate 210 preferably comprises a dielectric layer 220 in interfacial contact with a front surface thereof. The upper silicon layer of the multilayer structure is bonded to the dielectric layer 220 in interfacial contact with the front surface of the manipulating substrate 210. The manipulating substrate 210 comprises a semiconductor material selected from the group consisting of silicon, silicon carbide silicon-germanium, gallium arsenide, gallium nitride, indium phosphide, indium-gallium arsenide, germanium, and combinations thereof. The semiconductor manipulation substrate 210 comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor manipulation wafer and the other of which is a back surface of the handling substrate. a semiconductor edge, a circumferential edge joining the front and rear surfaces of the semiconductor manipulation substrate, and a volume region between the front and back surfaces of the semiconductor handling substrate. The semiconductor handling substrate. 210 is typically a slice having a nominal diameter of at least about 150 mm, at least about 200 mm, at least about 300 mm, or at least about 450 mm. The thicknesses of the manipulating substrate 210 may vary from about 250 micrometers to about 1500 micrometers, for example, from about 300 micrometers to about 1000 micrometers, suitably in the range of about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers. In some embodiments, the manipulating substrate 210 comprises monocrystalline silicon, which has been sliced from a monocrystalline ingot formed according to Czochralski crystal growth methods or conventional floating zone growth methods. The handling substrate comprises a dielectric layer 220. Suitable dielectric layers may comprise a material selected from silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof. In some embodiments, the dielectric layer has a thickness of at least about 5 nanometers, at least about 10 nanometers, for example between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or between about 100 nanometers and about 400 nanometers, such as about 50 nanometers, 100 nanometers, or 200 nanometers, or about 100 nanometers to about 800 nanometers, such as about 600 nanometers.
[0025] In some embodiments, the dielectric layer comprises one or more insulative materials selected from the group consisting of silicon dioxides, silicon nitride, silicon oxynitride, and any combination thereof. In some embodiments, the dielectric layer has a thickness of at least about 5 nanometers, at least about 10 nanometers, for example between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers, or 3036844 23 between about 100 nanometers and about 400 nanometers, such as about 50 nanometers, 100 nanometers, or 200 nanometers, or between about 100 nanometers and about 800 nanometers, such as about 600 nanometers.
[0026] In some embodiments, the dielectric layer comprises multiple layers of insulating material. The dielectric layer may comprise two insulating layers, three insulating layers, or more. Each insulating layer may comprise a material chosen from silicon dioxide, silicon oxynitride, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide and lanthanum oxide. , barium oxide, and a combination thereof. In some embodiments, each insulating layer may comprise a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and any combination thereof. Each insulating layer may have a thickness of at least about 5 nanometers, at least about 10 nanometers, for example between about 10 nanometers and about 10,000 nanometers, between about 10 nanometers and about 5,000 nanometers, between 50 nanometers and about 400 nanometers nanometers, or between about 100 nanometers and about 400 nanometers, such as about 50 nanometers, 100 nanometers, or 200 nanometers, or about 100 nanometers to about 800 nanometers, such as about 600 nanometers.
[0027] Since the mechanical bond between the silicon top layer of the multilayer structure and the dielectric layer 220 of the handling substrate is relatively weak, in some embodiments, the bonded structure can then be annealed to solidify the bond. In some embodiments of the present invention, the bonded structure is annealed at a temperature sufficient to form a thermally activated cleavage plane in the monocrystalline semiconductor donor substrate. An example of a suitable tool may be a simple box type furnace, such as a Blue M model. In some preferred embodiments, the bonded structure is annealed at a temperature of about 200 ° C to about 350 ° C. From about 225 ° C to about 325 ° C, preferably about 300 ° C. Thermal annealing can be conducted for a period of about 10 minutes to about 10 hours, preferably about 2 hours. Thermal annealing in these temperature ranges is sufficient to form a thermally activated cleavage plane. After thermal annealing to activate the cleavage plane, the bonded structure can be cleaved.
[0028] After thermal annealing, the bond between the upper silicon layer of the multilayer structure and the dielectric layer 220 of the handling substrate is strong enough to initiate a layer transfer by cleavage of the structure bonded to the cleavage plane. Cleavage can be carried out according to techniques known in the art. In some embodiments, the bonded structure may be placed in a conventional cleavage station, fixed on one side to stationary suction cups and secured on the other side by additional suction cups on an articulated arm. A crack is initiated near the attachment of the suction cups and the movable arm pivots around the hinge by cleaving the wafer. The cleavage separates a portion of the semiconductor donor wafer, so as to leave a semiconductor component layer, preferably a silicon component layer, on the semiconductor-on-insulator composite structure. After cleavage, the cleaved structure may be subjected to optional high-temperature annealing to further enhance the bonding between the transferred layer (comprising the upper layer of silicon, the layer comprising silicon and germanium, and a layer of etching stop comprising silicon) and the semiconductor handling substrate. An example of a suitable tool may be a vertical furnace such as an ASM A400. In some preferred embodiments, the bonded structure is annealed at a temperature of about 800 ° C to about 900 ° C, preferably about 850 ° C. The annealing temperature should be below the melting point of Ge, which is 938.2 ° C. Thermal annealing can be conducted for a period of about 0.5 hours to about 8 hours, preferably about 4 hours. Thermal annealing in these temperature ranges is sufficient to enhance the bond between the transferred component layer and the single crystal semiconductor handling substrate. After cleavage and annealing at high temperature, the bonded structure may be subjected to an etching process designed to remove excess material, including silicon-germanium. The layer comprising germanium, optionally with silicon, may be etched in solution. The etching agent only etches the layer 50 comprising germanium, optionally with silicon, selectively but does not etch the Si etch stop layer. A suitable etching solution is a solution of H 2 O 2 (comprising between 0.1 and 1 mole of hydrogen peroxide per liter of distilled water). The etching operation may be performed in a standard semiconductor fabrication cleaning device at room temperature or elevated temperature (e.g., between 50 and 70 ° C). Depending on the etching agent concentration and the temperature, the typical etching time is in the range of 30 seconds to 10 minutes. HCI may be added to the H202-containing etching agent to help remove metal contamination. In some embodiments, the bonded structure may be etched by submitting to a vapor phase HCI etching process in a horizontal flow single wafer epitaxial reactor using H 2 as a carrier gas. The silicon-germanium-on-insulator (SG01) structure 230 comprises a manipulation substrate 210, a dielectric layer 220, a thin layer of silicon, and a layer comprising germanium, optionally with silicon. Since the multilayer structure (exemplarily described in FIG. 1E) and represented by 110 in FIG. 2 further comprises additional pairs of a silicon etch stop layer and a layer comprising germanium, optionally with silicon, the process of ion implantation, bonding, cleavage and etching, so as to prepare an additional semiconductor on insulator 330, such as a germanium on insulator (Ge01) or silicon-germanium on insulator ( SG01), comprising a handling substrate 310, a dielectric layer 320, a thin layer of silicon, and a layer comprising germanium, optionally with silicon. The process may continue until the additional pairs of a silicon etch layer and a layer comprising germanium, optionally with silicon, are exhausted. Alternatively, the donor structure may be subjected to additional cycles of depositing pairs of a silicon etch layer and a layer comprising silicon and germanium. As the invention has been described in detail, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims. Since different modifications may be made in the above compositions and methods without departing from the scope of the invention, it should be noted that all the elements contained in the above description are to be interpreted as being illustrative and not in a limiting sense.
[0029] When introducing elements of the present invention or the preferred embodiment (s) thereof, the articles "a", "a", "the", and "said" are intended to mean that one or more of the elements are present. The terms "comprising", "comprising", and "having" are intended to be included and mean that additional elements other than the listed elements may be present.

权利要求:
Claims (33)
[0001]
REVENDICATIONS1. A process for preparing a multilayer structure, the method comprising: (a) depositing a first layer comprising germanium on a front surface of a silicon substrate, the silicon substrate comprising two major surfaces, generally parallel, of which one is the front surface of the silicon substrate and the other is a back surface of the silicon substrate, a circumferential edge joining the front and rear surfaces of the silicon substrate, a central plane between and parallel to the front surface and at the rear surface of the silicon substrate, a central axis perpendicular to the central plane, and a volume region between the front and rear surfaces of the silicon substrate, and further wherein the first layer comprising germanium has a thickness of between about 0 , 5 micrometers and about 100 microns, as measured along the central axis; (b) depositing a second layer comprising silicon on the first layer comprising germanium, the second layer comprising silicon having a thickness of between about 0.5 nanometer and about 5 nanometers, as measured along the central axis; and (c) depositing a third layer comprising germanium and optionally silicon on the second layer comprising silicon, the third layer comprising silicon and germanium having a formula SixGel_x, wherein x is between about 0 and about 0.8, in molar ratio and further the third layer comprising silicon and germanium having a thickness of at least about 1 nanometer.
[0002]
The method of claim 1 wherein steps (b) and (c) are repeated.
[0003]
The method of claim 1 wherein steps (b) and (c) are repeated at least two times.
[0004]
The method of claim 1 wherein the first layer comprising germanium has a thickness of between about 0.5 micrometer and about 50 micrometer, as measured along the central axis. 3036844 28
[0005]
The method of claim 1 wherein the first layer comprising germanium has a thickness of between about 1 micrometer and about 10 microns, as measured along the central axis. 5
[0006]
The method of claim 1 further comprising annealing the silicon substrate comprising the first layer comprising germanium at a temperature and for a time sufficient to reduce the amount of through dislocations. 10
[0007]
The method of claim 6 wherein the through-dislocation density is not greater than about 1x107 through-dislocations / cm 2.
[0008]
The method of claim 6 wherein the through dislocation density is not greater than about 1x106 through dislocations / cm 2. 15
[0009]
The method of claim 1 wherein the second layer comprising silicon has a thickness of between about 0.5 nanometers and about 20 nanometers, as measured along the central axis. 20
[0010]
The method of claim 1 wherein the third layer comprises germanium and silicon, and has a formula SixGel_x, wherein x is from about 0.1 to about 0.4, in molar ratio.
[0011]
The method of claim 1 wherein the third layer comprising germanium and optionally silicon has a thickness of between about 1 nanometer and about 1000 nanometers.
[0012]
The method of claim 1 wherein the third layer comprising germanium and optionally silicon has a thickness of between about 5 nanometers and about 300 nanometers.
[0013]
13. The method of claim 1 wherein each of the layers is deposited by epitaxial deposition.
[0014]
A process for preparing a semiconductor-on-insulator structure, the method comprising: forming a cleavage plane in a multilayer structure, the multilayer structure comprising (i) a silicon substrate comprising two major surfaces , generally parallel, one of which is a front surface of the silicon substrate and the other of which is a rear surface of the silicon substrate, a circumferential edge joining the front and rear surfaces of the silicon substrate, a central plane between and parallel to the front surface and the rear surface of the silicon substrate, a central axis perpendicular to the central plane, and a volume region between the front and rear surfaces of the silicon substrate, (ii) a germanium layer in interfacial contact with the surface before the silicon substrate, (iii) at least one pair of layers in interfacial contact with the germanium layer, each pair of layers comprising a layer silicon and a layer comprising germanium and optionally silicon having a formula SixGel_x, wherein x is from about 0 to about 0.8, in molar ratio, and (iv) a passivation layer of silicon in contact with at least a pair of layers, wherein the cleavage plane is formed in at least one pair of layers comprising the silicon layer and the silicon-germanium layer; and bonding the multilayer structure at a dielectric layer interfacial contact with a front surface of a semiconductor manipulation substrate, the semiconductor manipulation substrate comprising two major, generally parallel, surfaces one is the front surface of the semiconductor handling wafer and the other is a back surface of the semiconductor manipulation substrate, a circumferential edge joining the front and rear surfaces of the semiconductor handling substrate, and a volume region between the front and rear surfaces of the semiconductor handling substrate.
[0015]
The method of claim 14 wherein the multilayer structure comprises at least two pairs of layers comprising the silicon layer and the layer comprising germanium and optionally silicon. 30
[0016]
The method of claim 14 wherein the cleavage plane is formed by: implanting ions into the multilayer structure, wherein the ions are implanted through the silicon passivation layer to a maximum concentration depth of ions implanted in at least one pair of layers comprising the silicon layer and the layer comprising germanium and optionally silicon; and 3036844 annealing the multilayered structure at a temperature and for a time sufficient to form the cleavage plane at or near the maximum concentration depth of implanted ions. 5
[0017]
The method of claim 16 wherein the implanted ions are selected from the group consisting of hydrogen, helium, and a combination thereof.
[0018]
18. The method of claim 14 wherein the germanium layer has a thickness of from about 0.5 micrometers to about 100 micrometers as measured along the central axis.
[0019]
The method of claim 14 wherein the silicon layer has a thickness of between about 0.5 nanometers and about 5 nanometers, as measured along the central axis. 15
[0020]
20. The method of claim 14 wherein the layer comprising germanium and optionally silicon has a formula SixGel_x, wherein x is from about 0.1 to about 0.4, in molar ratio. 20
[0021]
The method of claim 14 wherein the layer comprising germanium and optionally silicon has a thickness of between about 1 nanometer and about 1000 nanometers.
[0022]
22. The method of claim 14 further comprising cleaving the multilayer structure at the cleavage plane in whichat least one pair of layers comprising the silicon layer and the layer comprising germanium and optionally silicon so as to prepare a semiconductor-on-insulator structure comprising the semiconductor manipulation substrate, the dielectric layer, the silicon passivation layer, and at least a portion of the layer pair comprising the silicon layer and the layer comprising germanium and optionally silicon.
[0023]
23. The method of claim 22 further comprising etching and smoothing the cleaved portion of the pair of layers comprising the silicon layer and the layer comprising germanium and optionally silicon. 3036844 31
[0024]
24. A multilayer structure comprising: (i) a silicon substrate comprising two major surfaces, generally parallel, one of which is a front surface of the silicon substrate and the other of which is a rear surface of the silicon substrate, a circumferential edge; Assembling the front and rear surfaces of the silicon substrate, a central plane between and parallel to the front surface and the rear surface of the silicon substrate, a central axis perpendicular to the central plane, and a volume region between the front and rear surfaces of the silicon substrate; silicon substrate, (ii) a germanium layer in interfacial contact with the front surface of the silicon substrate, (iii) at least one pair of layers in interfacial contact with the germanium layer, each pair of layers comprising a layer of silicon, silicon and a layer comprising germanium and optionally silicon having a formula SixGel_x, wherein x is from about 0 to about 0.8, in which molar, and (iv) a silicon passivation layer in contact with at least one pair of layers.
[0025]
25. The multilayer structure of claim 24 comprising at least two pairs of layers comprising the silicon layer and the layer comprising germanium and optionally silicon.
[0026]
The multilayer structure of claim 24 wherein the germanium layer has a thickness of between about 0.5 micrometer and about 50 micrometer, as measured along the central axis.
[0027]
The multilayer structure of claim 24 wherein the germanium layer has a thickness of from about 1 micron to about 10 microns, as measured along the central axis. 30
[0028]
The multilayer structure of claim 24 wherein the germanium layer has a through-dislocation density of not more than about 1x107 through-dislocations / cm 2. 3036844 32
[0029]
The multilayer structure of claim 24 wherein the germanium layer has a through-dislocation density of not more than about 1x106 through-dislocations / cm 2. 5
[0030]
The multilayer structure of claim 24 wherein the silicon layer of at least one pair of layers has a thickness of between about 0.5 nanometers and about 5 nanometers, as measured along the central axis.
[0031]
31. The multilayer structure of claim 24 wherein the layer comprising germanium and silicon has a formula SixGel_x, wherein x is from about 0.1 to about 0.4, in molar ratio.
[0032]
The multilayer structure of claim 24 wherein the layer comprising germanium and optionally silicon has a thickness of between about 1 nanometer and about 1000 nanometers.
[0033]
The multilayer structure of claim 24 wherein the layer comprising germanium and optionally silicon has a thickness of between about 5 nanometers and about 300 nanometers.

类似技术:

公开号 | 公开日 | 专利标题

JP6650463B2|2020-02-19|Method of manufacturing high resistivity semiconductor-on-insulator wafer with charge trapping layer

JP6980071B2|2021-12-15|High resistivity silicon on-insulator substrate with improved charge capture efficiency

US10818539B2|2020-10-27|Manufacturing method of smoothing a semiconductor surface

EP1733423A1|2006-12-20|Heat treatment for improving the quality of a taken thin layer

FR3030877B1|2019-11-08|FABRICATION OF GROUP IIIA NITRIDE LAYERS ON SEMICONDUCTOR STRUCTURES ON INSULATION

TWI727123B|2021-05-11|High resistivity silicon-on-insulator structure and method of manufacture thereof

FR3033933A1|2016-09-23|THERMALLY STABLE LOAD TRAP LAYER FOR USE IN THE MANUFACTURE OF SEMICONDUCTOR STRUCTURES ON INSULATION

US20170256442A1|2017-09-07|Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof

FR3036844A1|2016-12-02|METHOD OF MANUFACTURING SEMICONDUCTOR ON INSULATION

EP2043135A1|2009-04-01|Method of manufacturing semiconductor structures useful for the production of semiconductor-on-insulator substrates, and its applications

EP3427293B1|2021-05-05|Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof

TWI709175B|2020-11-01|Silicon germanium-on-insulator structure

CN107873106B|2022-03-18|Method for fabricating silicon germanium on insulator

TW202205372A|2022-02-01|High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency

FR2886457A1|2006-12-01|METHOD FOR MANUFACTURING THICKENED OXIDE LAYER STRUCTURE, ESPECIALLY ON GE OR SIG SUBSTRATE

同族专利:

公开号 | 公开日

WO2016196060A1|2016-12-08|

US20180294182A1|2018-10-11|

FR3036844B1|2021-01-29|

CN107667416A|2018-02-06|

US10304722B2|2019-05-28|

JP6592534B2|2019-10-16|

TW201703204A|2017-01-16|

TWI698960B|2020-07-11|

CN107667416B|2021-08-31|

JP2018520509A|2018-07-26|

引用文献:

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

US4501060A|1983-01-24|1985-02-26|At&T Bell Laboratories|Dielectrically isolated semiconductor devices|

US4755865A|1986-01-21|1988-07-05|Motorola Inc.|Means for stabilizing polycrystalline semiconductor layers|

JP2617798B2|1989-09-22|1997-06-04|三菱電機株式会社|Stacked semiconductor device and method of manufacturing the same|

US6043138A|1996-09-16|2000-03-28|Advanced Micro Devices, Inc.|Multi-step polysilicon deposition process for boron penetration inhibition|

US5783469A|1996-12-10|1998-07-21|Advanced Micro Devices, Inc.|Method for making nitrogenated gate structure for improved transistor performance|

US6306729B1|1997-12-26|2001-10-23|Canon Kabushiki Kaisha|Semiconductor article and method of manufacturing the same|

US6068928A|1998-02-25|2000-05-30|Siemens Aktiengesellschaft|Method for producing a polycrystalline silicon structure and polycrystalline silicon layer to be produced by the method|

US6268068B1|1998-10-06|2001-07-31|Case Western Reserve University|Low stress polysilicon film and method for producing same|

JP4313874B2|1999-02-02|2009-08-12|キヤノン株式会社|Substrate manufacturing method|

US6372600B1|1999-08-30|2002-04-16|Agere Systems Guardian Corp.|Etch stops and alignment marks for bonded wafers|

US20020090758A1|2000-09-19|2002-07-11|Silicon Genesis Corporation|Method and resulting device for manufacturing for double gated transistors|

US6890835B1|2000-10-19|2005-05-10|International Business Machines Corporation|Layer transfer of low defect SiGe using an etch-back process|

US6562127B1|2002-01-16|2003-05-13|The United States Of America As Represented By The Secretary Of The Navy|Method of making mosaic array of thin semiconductor material of large substrates|

US7074623B2|2002-06-07|2006-07-11|Amberwave Systems Corporation|Methods of forming strained-semiconductor-on-insulator finFET device structures|

US6995430B2|2002-06-07|2006-02-07|Amberwave Systems Corporation|Strained-semiconductor-on-insulator device structures|

WO2004021420A2|2002-08-29|2004-03-11|Massachusetts Institute Of Technology|Fabrication method for a monocrystalline semiconductor layer on a substrate|

US7057234B2|2002-12-06|2006-06-06|Cornell Research Foundation, Inc.|Scalable nano-transistor and memory using back-side trapping|

DE602004020181D1|2003-01-07|2009-05-07|Soitec Silicon On Insulator|RECYCLING A WATER WITH A MULTILAYER STRUCTURE AFTER REMOVING A THIN LAYER|

WO2005031842A2|2003-09-26|2005-04-07|Universite Catholique De Louvain|Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses|

US7084460B2|2003-11-03|2006-08-01|International Business Machines Corporation|Method for fabricating SiGe-on-insulator and Ge-on-insulator substrates|

US6992025B2|2004-01-12|2006-01-31|Sharp Laboratories Of America, Inc.|Strained silicon on insulator from film transfer and relaxation by hydrogen implantation|

US6893936B1|2004-06-29|2005-05-17|International Business Machines Corporation|Method of Forming strained SI/SIGE on insulator with silicon germanium buffer|

US7279400B2|2004-08-05|2007-10-09|Sharp Laboratories Of America, Inc.|Method of fabricating single-layer and multi-layer single crystalline silicon and silicon devices on plastic using sacrificial glass|

US7312487B2|2004-08-16|2007-12-25|International Business Machines Corporation|Three dimensional integrated circuit|

US7476594B2|2005-03-30|2009-01-13|Cree, Inc.|Methods of fabricating silicon nitride regions in silicon carbide and resulting structures|

US20070117350A1|2005-08-03|2007-05-24|Memc Electronic Materials, Inc.|Strained silicon on insulator with layer transfer from oxidized donor|

FR2890489B1|2005-09-08|2008-03-07|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE HETEROSTRUCTURE ON INSULATION|

US7638410B2|2005-10-03|2009-12-29|Los Alamos National Security, Llc|Method of transferring strained semiconductor structure|

FR2902233B1|2006-06-09|2008-10-17|Soitec Silicon On Insulator|METHOD FOR LIMITING LACUNAR MODE BROADCAST DISTRIBUTION IN A HETEROSTRUCTURE|

FR2910702B1|2006-12-26|2009-04-03|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING A MIXED SUBSTRATE|

US20080251814A1|2007-04-16|2008-10-16|International Business Machines Corporation|Hetero-bonded semiconductor-on-insulator substrate with an unpinning dielectric layer|

JP4445524B2|2007-06-26|2010-04-07|株式会社東芝|Manufacturing method of semiconductor memory device|

JP2009016692A|2007-07-06|2009-01-22|Toshiba Corp|Manufacturing method of semiconductor storage device, and semiconductor storage device|

FR2921515B1|2007-09-25|2010-07-30|Commissariat Energie Atomique|METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURES USEFUL FOR PRODUCING SEMICONDUCTOR-OVER-INSULATING SUBSTRATES, AND APPLICATIONS THEREOF|

US7915716B2|2007-09-27|2011-03-29|Stats Chippac Ltd.|Integrated circuit package system with leadframe array|

US7879699B2|2007-09-28|2011-02-01|Infineon Technologies Ag|Wafer and a method for manufacturing a wafer|

US8128749B2|2007-10-04|2012-03-06|International Business Machines Corporation|Fabrication of SOI with gettering layer|

US7868419B1|2007-10-18|2011-01-11|Rf Micro Devices, Inc.|Linearity improvements of semiconductor substrate based radio frequency devices|

US7998835B2|2008-01-15|2011-08-16|Globalfoundries Singapore Pte. Ltd.|Strain-direct-on-insulator substrate and method of forming|

US20090236689A1|2008-03-24|2009-09-24|Freescale Semiconductor, Inc.|Integrated passive device and method with low cost substrate|

FR2933234B1|2008-06-30|2016-09-23|S O I Tec Silicon On Insulator Tech|GOODLY DUAL STRUCTURE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME|

US8642416B2|2010-07-30|2014-02-04|Monolithic 3D Inc.|Method of forming three dimensional integrated circuit devices using layer transfer technique|

US8058137B1|2009-04-14|2011-11-15|Monolithic 3D Inc.|Method for fabrication of a semiconductor device and structure|

US9099526B2|2010-02-16|2015-08-04|Monolithic 3D Inc.|Integrated circuit device and structure|

JP2010258083A|2009-04-22|2010-11-11|Panasonic Corp|Soi wafer, method for producing the same, and method for manufacturing semiconductor device|

DE112010004241T5|2009-11-02|2013-05-08|Fuji Electric Co., Ltd.|Semiconductor component and method for producing the semiconductor device|

JP5644096B2|2009-11-30|2014-12-24|ソニー株式会社|Method for manufacturing bonded substrate and method for manufacturing solid-state imaging device|

US8252624B2|2010-01-18|2012-08-28|Applied Materials, Inc.|Method of manufacturing thin film solar cells having a high conversion efficiency|

US8859393B2|2010-06-30|2014-10-14|Sunedison Semiconductor Limited|Methods for in-situ passivation of silicon-on-insulator wafers|

JP5627649B2|2010-09-07|2014-11-19|株式会社東芝|Method for manufacturing nitride semiconductor crystal layer|

JP5117588B2|2010-09-07|2013-01-16|株式会社東芝|Method for manufacturing nitride semiconductor crystal layer|

FR2967812B1|2010-11-19|2016-06-10|S O I Tec Silicon On Insulator Tech|ELECTRONIC DEVICE FOR RADIOFREQUENCY OR POWER APPLICATIONS AND METHOD OF MANUFACTURING SUCH A DEVICE|

US9287353B2|2010-11-30|2016-03-15|Kyocera Corporation|Composite substrate and method of manufacturing the same|

US8536021B2|2010-12-24|2013-09-17|Io Semiconductor, Inc.|Trap rich layer formation techniques for semiconductor devices|

US8481405B2|2010-12-24|2013-07-09|Io Semiconductor, Inc.|Trap rich layer with through-silicon-vias in semiconductor devices|

US8466036B2|2010-12-24|2013-06-18|Io Semiconductor, Inc.|Trap rich layer for semiconductor devices|

US8796116B2|2011-01-31|2014-08-05|Sunedison Semiconductor Limited|Methods for reducing the metal content in the device layer of SOI structures and SOI structures produced by such methods|

US20120235283A1|2011-03-16|2012-09-20|Memc Electronic Materials, Inc.|Silicon on insulator structures having high resistivity regions in the handle wafer|

FR2973159B1|2011-03-22|2013-04-19|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING BASE SUBSTRATE|

FR2973158B1|2011-03-22|2014-02-28|Soitec Silicon On Insulator|METHOD FOR MANUFACTURING SEMICONDUCTOR-TYPE SUBSTRATE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS|

US9496255B2|2011-11-16|2016-11-15|Qualcomm Incorporated|Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same|

US8741739B2|2012-01-03|2014-06-03|International Business Machines Corporation|High resistivity silicon-on-insulator substrate and method of forming|

CN103219275B|2012-01-19|2016-03-23|中国科学院上海微系统与信息技术研究所|There is the preparation method of SGOI or sSOI of high relaxation and fabricating low-defect-density|

US20130193445A1|2012-01-26|2013-08-01|International Business Machines Corporation|Soi structures including a buried boron nitride dielectric|

US8921209B2|2012-09-12|2014-12-30|International Business Machines Corporation|Defect free strained silicon on insulator substrates|

US8748940B1|2012-12-17|2014-06-10|Intel Corporation|Semiconductor devices with germanium-rich active layers and doped transition layers|

US9202711B2|2013-03-14|2015-12-01|Sunedison Semiconductor Limited |Semiconductor-on-insulator wafer manufacturing method for reducing light point defects and surface roughness|

US8951896B2|2013-06-28|2015-02-10|International Business Machines Corporation|High linearity SOI wafer for low-distortion circuit applications|

US9768056B2|2013-10-31|2017-09-19|Sunedison Semiconductor Limited |Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition|

US9536736B2|2015-02-04|2017-01-03|International Business Machines Corporation|Reducing substrate bowing caused by high percentage sige layers|

WO2016140850A1|2015-03-03|2016-09-09|Sunedison Semiconductor Limited|Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress|DE102016112139B3|2016-07-01|2018-01-04|Infineon Technologies Ag|A method of reducing an impurity concentration in a semiconductor body|

WO2018080772A1|2016-10-26|2018-05-03|Sunedison Semiconductor Limited|High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency|

CN109119331B|2017-06-23|2021-02-02|上海新昇半导体科技有限公司|Semiconductor device, manufacturing method thereof and electronic device|

法律状态:
2017-06-27| PLFP| Fee payment|Year of fee payment: 2 |

2018-04-06| PLSC| Search report ready|Effective date: 20180406 |

2018-06-26| PLFP| Fee payment|Year of fee payment: 3 |

2019-06-25| PLFP| Fee payment|Year of fee payment: 4 |

2019-08-30| TP| Transmission of property|Owner name: GLOBALWAFERS CO., LTD, TW Effective date: 20190531 |

2020-06-25| PLFP| Fee payment|Year of fee payment: 5 |

2021-06-25| PLFP| Fee payment|Year of fee payment: 6 |

优先权:

申请号 | 申请日 | 专利标题

US201562169173P| true| 2015-06-01|2015-06-01|

[返回顶部]